A Phase-Locked Loop with Saturated Estimator for Single-Phase Grid Synchronization

This paper proposes a phase-locked-loop (PLL) with saturated estimation of the fundamental frequency. The overall PLL design consists of a third order system, where two parts could be identif ed. The f rst part represents the oscillating vector, a second order system, whose state variables are the voltage estimate signal and an estimate of a signal in quadrature (90 degrees behind and with same amplitude as the voltage estimate). The second part, represents an estimator of the fundamental frequency, which is proposed to be a saturated integrator in order to keep the fundamental frequency inside a given interval in a soft manner. The paper also presents a sketch of the convergence and stability proof of the proposed scheme. The proof is based on a time scale separation assumption, i.e., it assumes that the dynamics of the harmonic oscillator is faster than the dynamics of the frequency estimator. The performance is evaluated by simulations.