An Efficient Self-Powered Piezoelectric Energy Harvesting CMOS Interface Circuit Based on Synchronous Charge Extraction Technique

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659 mu W when the piezoelectric transducer original opencircuit voltage V-oc,V-org = 5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V-DC. The harvesting efficiency can still reach 71.3% at V-oc,V-org = 5 V. The size of the active area is 0.5 mm(2) in a 0.18-mu m CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things.