A 24-GHz High Linearity Down-conversion Mixer in 90-nm CMOS

被引：0

作者：

Chen, Feifei ^{[1
]}

Wang, Yunshan ^{[1
]}

Lin, Jung-Lin ^{[1
]}

Tsai, Zuo-Min ^{[2
]}

Wang, Huei ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Commun Engn, Taipei, Taiwan

[2] Natl Chung Cheng Univ, Dept Elect Engn, Chiayi, Taiwan

来源：

2018 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT) | 2018年

关键词：

CMOS; mixer; folded architecture; LINEARIZATION; RECEIVER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 24-GHz high linearity down-conversion mixer in 90-nm CMOS is presented in this paper. The mixer utilizes folded architecture, LC tank, distributed derivative superposition (DS) linearization technique to achieve high linearity with relatively low power. The mixer achieves 0 dBm IP1dB. The mixer provides -3 dB conversion gain and the IIP3 is 21 dBm with only 10-mW dc consumption.

引用

页码：73 / 75

页数：3

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