A Low Conduction Loss Modular Multilevel Converter Topology With DC Fault Blocking Capability and Reduced Capacitance

被引:11
|
作者
Peng, Cheng [1 ]
Li, Rui [1 ]
机构
[1] Shanghai Jiao Tong Univ, Sch Elect Informat & Elect Engn, Dept Elect Engn, Shanghai 200240, Peoples R China
基金
中国国家自然科学基金;
关键词
Topology; Circuit faults; Insulated gate bipolar transistors; Bridge circuits; Capacitance; Fault currents; Capacitors; Capacitance reduction; fault protection; HVDC transmission; modular multilevel converters; SUBMODULE; DESIGN; CELLS; VSC; MMC;
D O I
10.1109/TCSII.2019.2932329
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new modular multilevel converter (MMC) sub-module (SM) topology based on the reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed in this brief for equipping the system with dc fault blocking capability. In addition, the proposed topology has lower conduction loss than all of the existing SM topologies with dc side fault blocking capability. By employing RB-IGBTs in the sub-module circuit, it is possible to change the fault current path to block the dc side fault without inserting extra semiconductor devices in the normal current path, thus reducing the conduction loss when compared to other topologies. A comparison between the proposed topology and the existing topologies in terms of components number, power loss and dc fault blocking capability is carried out to show the superiority of the proposed topology. To reduce the cost of the topology, a control strategy is introduced to reduce the capacitance of the proposed topology. By optimizing the amplitude of the second-order and fourth-order harmonic currents when injecting third-order harmonic voltage, the capacitance can be reduced to about 37% of that of the conventional method. To verify the dc side fault blocking capability and the effect of the proposed method, the controller hardware in the loop experiment based on RT-LAB is conducted. The reported study results confirm the dc side fault riding through capability of the proposed sub-module topology and the effectiveness of the proposed method is also validated.
引用
收藏
页码:1299 / 1303
页数:5
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