Tutorial: Fabrication and three-dimensional integration of nanoscale memristive devices and

被引:11
|
作者
Lin, Peng [1 ,2 ,3 ]
Xia, Qiangfei [1 ]
机构
[1] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA
[2] MIT, Dept Mech Engn, Cambridge, MA 02139 USA
[3] MIT, Elect Res Lab, Cambridge, MA 02139 USA
关键词
IMPRINT LITHOGRAPHY; CLASSIFICATION; MEMORIES; PITCH;
D O I
10.1063/1.5038109
中图分类号
O59 [应用物理学];
学科分类号
摘要
To catch up with growing complexity of artificial neural networks, hybrid integrated systems with high-density nanoscale memristive devices have been proposed as building blocks for the next generation computing hardware. In this Tutorial, we first introduce the methodologies in fabrication of memristor crossbars with a sub-10 nm feature size, including nanoimprint lithography that provides excellent resolution at low cost. Technical issues such as critical dimension control, overlay alignment accuracy, and reliable mold cleaning are discussed in detail. In the meantime, as lateral scaling becomes more challenging, three-dimensional (3D) integration presents an alternative solution to further increase the packing density and to provide new functionalities. Some early demonstrations of 3D hybrid memristor/complementary metal oxide semiconductor circuits are reviewed here, and their design and fabrication related issues are discussed. Successful implementation of large-scale 3D memristive systems with nanometer scale devices may provide ultimate solution to the hardware bottleneck for future computing applications. Published by AIP Publishing.
引用
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页数:13
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