Specifying urgency in timed I/O automata

被引:7
|
作者
Gebremichael, B [1 ]
Vaandrager, F [1 ]
机构
[1] Radboud Univ Nijmegen, Inst Comp & Informat Sci, Nijmegen, Netherlands
关键词
D O I
10.1109/SEFM.2005.42
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
Tools and techniques based on timed automata (such as Uppaal and the timed I/O automata framework) have proven to be extremely useful for the analysis of protocols and control software for real-time systems. However a significant limitation of these approaches is that, due to the expressiveness of the modeling languages, timelocks - degenerate states in which time is unable to pass - can freely arise and cannot, in the general case, be detected. As a remedy to this problem Sifakis et al. advocate the use of deadline predicates for the specification of progress properties of Alur-Dill style timed automata. In this article, we extend these ideas to a more general setting, which may serve as a basis for deductive verification techniques. More specifically, we extend the TIOA framework of Lynch et al with urgency predicates. We identify a suitable language to describe the resulting timed I/O automata with urgency and show that for this language time reactivity holds by construction. We also establish that the class of timed I/O automata with urgency is closed under composition. The use of urgency predicates is compared with three alternative approaches to specifying progress properties that have been advocated in the literature: invariants, stopping conditions and deadline predicates. We argue that in practice the use of urgency predicates leads to shorter and more natural specifications than any of the other approaches. Some preliminary results on proving invariant properties of timed (I/O) automata with urgency are presented.
引用
收藏
页码:64 / 73
页数:10
相关论文
共 50 条
  • [1] Specifying and proving properties of timed I/O automata using Tempo
    Myla Archer
    Hongping Lim
    Nancy Lynch
    Sayan Mitra
    Shinya Umeno
    [J]. Design Automation for Embedded Systems, 2008, 12 : 139 - 170
  • [2] Specifying and proving properties of timed I/O automata using Tempo
    Archer, Myla
    Lim, Hongping
    Lynch, Nancy
    Mitra, Sayan
    Umeno, Shinya
    [J]. DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 2008, 12 (1-2) : 139 - 170
  • [3] Specifying and proving properties of Timed I/O Automata in the TIOA toolkit
    Archer, Myla
    Lim, HongPing
    Lynch, Nancy
    Mitra, Sayan
    Umeno, Shinya
    [J]. FOURTH ACM & IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CO-DESIGN, PROCEEDINGS, 2006, : 129 - +
  • [4] Decomposing verification of timed I/O automata
    Kaynar, DK
    Lynch, N
    [J]. FORMAL TECHNIQUES, MODELLING AND ANALYSIS OF TIMED AND FAULT-TOLERANT SYSTEMS, PROCEEDINGS, 2004, 3253 : 84 - 101
  • [5] Effective conformance testing of timed I/O automata
    Zhao, Dong
    Ye, Kejiang
    [J]. Zhengzhou Daxue Xuebao/Journal of Zhengzhou University, 2002, 34 (04):
  • [6] Keynote Abstract Timed and Probabilistic I/O Automata
    Lynch, Nancy
    [J]. 2013 28TH ANNUAL IEEE/ACM SYMPOSIUM ON LOGIC IN COMPUTER SCIENCE (LICS), 2013, : 12 - 12
  • [7] From I/O automata to timed I/O automata -: A solution to the 'Generalized Railroad Crossing' in Isabelle/HOLCF
    Grobauer, B
    Müller, O
    [J]. THEOREM PROVING IN HIGHER ORDER LOGICS, PROCEEDINGS, 1999, 1690 : 273 - 289
  • [8] Synthesising Optimal Timing Delays for Timed I/O Automata
    Diciolla, Marco
    Kim, Chang Hwan Peter
    Kwiatkowska, Marta
    Mereacre, Alexandru
    [J]. 2014 INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE (EMSOFT), 2014,
  • [9] Specifying BPMN diagrams with Timed Automata Proposal of some mapping rules
    Mendoza Morales, Luis Eduardo
    [J]. PROCEEDINGS OF THE 2014 9TH IBERIAN CONFERENCE ON INFORMATION SYSTEMS AND TECHNOLOGIES (CISTI 2014), 2014,
  • [10] Trace-based semantics for probabilistic timed I/O automata
    Mitra, Sayan
    Lynch, Nancy
    [J]. HYBRID SYSTEMS: COMPUTATION AND CONTROL, PROCEEDINGS, 2007, 4416 : 718 - +