A hardware implementation of intelligent ECG classifier

被引:2
|
作者
Hoai Linh Tran [1 ]
Van Nam Pham [1 ]
Duc Thao Nguyen [2 ]
机构
[1] Hanoi Univ Sci & Technol, Dept Elect Engn, Hanoi, Vietnam
[2] Sao Do Univ, Dept Elect & Telecommun, Hanoi, Vietnam
关键词
PSoC; ECG classifier; FPAA; Heart arrhythmia; Hermite functions; TSK neuro-fuzzy network; Heart beat classification; Programmable IC;
D O I
10.1108/COMPEL-05-2014-0119
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Purpose - The purpose of this paper is to design an intelligent ECG classifier using programmable IC technologies to implement many functional blocks of signal acquisition and processing in one compact device. The main microprocessor also simulates the TSK neuro-fuzzy classifier in testing mode to recognize the ECG beats. The design brings various theoretical solutions into practical applications. Design/methodology/approach - The ECG signals are acquired and pre-processed using the Field-Programmable Analog Array (FPAA) IC due to the ability of precise configuration of analog parameters. The R peak of the QRS complexes and a window of 300 ms of ECG signals around the R peak are detected. In this paper we have proposed a method to extract the signal features using the Hermite decomposition algorithm, which requires only a multiplication of two matrices. Based on the features vectors, the ECG beats are classified using a TSK neuro-fuzzy network, whose parameters are trained earlier on PC and downloaded into the device. The device performance was tested with the ECG signals from the MIT-BIH database to prove the correctness of the hardware implementations. Findings - The FPAA and Programmable System on Chip (PSoC) technologies allow us to integrate many signal processing blocks in a compact device. In this paper the device has the same performance in ECG signal processing and classifying as achieved on PC simulators. This confirms the correctness of the implementation. Research limitations/implications - The device was fully tested with the signals from the MIT-BIH databases. For new patients, we have tested the device in collecting the ECG signals and QRS detections. We have not created a new database of ECG signals, in which the beats are examined by doctors and annotated the type of the rhythm (normal or abnormal, which type of arrhythmia, etc.) so we have not tested the classification mode of the device on real ECG signals. Social implications - The compact design of an intelligent ECG classifier offers a portable solution for patients with heart diseases, which can help them to detect the arrhythmia on time when the doctors are not nearby. This type of device not only may help to improve the patients' safety but also contribute to the smart, inter-networked life style. Originality/value - The device integrate a number of solutions including software, hardware and algorithms into a single, compact device. Thank to the advance of programmable ICs such as FPAA and PSoC, the designed device can acquire one channel of ECG signals, extract the features and classify the arrhythmia type (if detected) using the neuro-fuzzy TSK network in online mode.
引用
收藏
页码:905 / 919
页数:15
相关论文
共 50 条
  • [1] Implementation of an Intelligent EMG Signal Classifier Using Open-Source Hardware
    Cardenas-Bolano, Nelson
    Polo, Aura
    Robles-Algarin, Carlos
    [J]. COMPUTERS, 2023, 12 (12)
  • [2] Hardware Implementation and Reduction of Artifacts from ECG Signal
    Gupta, Aman
    Chaskar, U. M.
    [J]. 2015 IEEE INTERNATIONAL CONFERENCE ON INFORMATION PROCESSING (ICIP), 2015, : 155 - 159
  • [3] Hardware Implementation of Naive Bayes Classifier: A Cost Effective Technique
    Seth, Himanshu Ranjan
    Banka, Haider
    [J]. 2016 3rd International Conference on Recent Advances in Information Technology (RAIT), 2016, : 264 - 267
  • [4] Hardware-in-the-loop Implementation of Residential Intelligent Microgrid
    Jia, Youwei
    He, Yufei
    Lyu, Xue
    Chai, Songjian
    Xu, Zhao
    Chen, Minghua
    [J]. 2018 IEEE POWER & ENERGY SOCIETY GENERAL MEETING (PESGM), 2018,
  • [5] Hardware Design and Implementation of an Intelligent Haptic Robotic Glove
    Popescu, Nirvana
    Popescu, Decebal
    Cozma, Alexandru
    Vaduva, Alexandru Jan
    [J]. 2014 INTERNATIONAL CONFERENCE AND EXPOSITION ON ELECTRICAL AND POWER ENGINEERING (EPE), 2014, : 174 - 177
  • [6] An intelligent image processing sensor -: the algorithm and the hardware implementation
    Wojcikowski, Marek
    Zaglewski, Robert
    Pankiewicz, Bogdan
    [J]. PROCEEDINGS OF THE 2008 1ST INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY, 2008, : 377 - 380
  • [7] New algorithm for selforganizing neural classifier suitable for easy hardware implementation
    Przylucki, S
    Plachecki, K
    Duk, M
    [J]. PHOTONICS APPLICATIONS IN ASTRONOMY, COMMUNICATIONS, INDUSTRY, AND HIGH-ENERGY PHYSICS EXPERIMENTS, 2003, 5125 : 402 - 408
  • [8] Hardware Implementation of Support Vector Machine Classifier using Reconfigurable Architecture
    Kumar, Santosh
    Manikandan, J.
    Agrawal, V. K.
    [J]. 2017 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2017, : 45 - 50
  • [9] Hardware Implementation of an efficient FIR filter for ECG Signal Denoising Application
    Ajaydas, U. R.
    Reddy, B. Naresh Kumar
    James, Alex
    [J]. 2022 29TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (IEEE ICECS 2022), 2022,
  • [10] Hybrid intelligent aircraft landing controller and its hardware implementation
    Juang, Jih-Gau
    Lin, Bo-Shian
    [J]. ADVANCES IN NATURAL COMPUTATION, PT 2, 2006, 4222 : 972 - 981