Mitigating DDoS Flooding Attacks against IoT using Custom Hardware Modules

被引:5
|
作者
Brasilino, Lucas R. B. [1 ]
Swany, Martin [1 ]
机构
[1] Indiana Univ, Sch Informat Comp & Engn, 700 N Woodlawn Ave, Bloomington, IN 47408 USA
关键词
Internet of Things; IoT; FPGA; Programmable Logic; Embedded Systems; CoAP; Security; Resilience; INTERNET;
D O I
10.1109/iotsms48152.2019.8939176
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The increasing number of deployed Internet of Things (IoT) devices is supporting a plethora of new applications that enriches our daily lives. Smart Cities, for instance, leverage IoT to enable new ways of interactions among citizens, government, public services, healthcare, natural resources, waste and energy management. This synergy pushes the participation of individuals and organizations to new levels, strengthening democracy. However, the ubiquity of such devices and their unique characteristics of being numerous, constantly connected to the Internet and having constrained processing capabilities turned IoT into the new target of cyberattacks. Lately, we have witnessed an alarming increase in attack events towards IoT. The most common pattern is usually done in two phases. In the first phase, attackers exploit vulnerabilities in as many devices as possible, turning them into their bots. In the second phase, attackers order bots to dispatch as many request as possible towards a chosen target, flooding them with requests, attempting to exhaust device's computing resources: a Distributed Denial of Service (DDoS) is in place. The traditional targets of massive DDoS attacks are eminent organizations, like financial institutions, governments and online retailers. However, there is space still for small scale DDoS attacks towards IoT devices itself. The main objective would be bringing down IoT devices which firmwares are not easily exploitable, such as security/video surveillance devices. In this paper, we present a study on DDoS flooding attack mitigation where IoT devices are the targets. To that end, we propose a feasible architecture leveraging a CoAP Accelerator to effectively improve device's resilience. The CoAP Accelerator works in cooperation with the device's CPU, having a key role on CoAP message processing. The architecture was prototyped in a System-on-Chip (SoC) Field Programmable Gate Array (FPGA) and evaluations were carried out demonstrating how device's computing resources are not exhausted, thus allowing it to proper operate while under attack.
引用
收藏
页码:58 / 64
页数:7
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