A 10-bit 2GHz current-steering CMOS D/A converter

被引：5
|
作者：
Yuan, Ling [1 ]
Ni, Weining [1 ]
Shi, Yin [1 ]
Dai, Foster F. [2 ]
机构：
[1] Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China
[2] Auburn Univ, Dept Elect & Comp Engn, Auburn, AL 36849 USA
来源：
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年
关键词：
D O I：
10.1109/ISCAS.2007.377991
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.
引用
收藏
页码：737 / +
页数：2
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