On-chip System Level Protection of FM Antenna Pin

被引:0
|
作者
Notermans, Guido [1 ]
Maksimovic, Dejan [1 ]
Vermont, Gerd [2 ]
van Maasakkers, Michiel [3 ]
Pusa, Fredrik [4 ]
Smedes, Theo [5 ]
机构
[1] ST Ericsson, Binzstr 38, CH-8045 Zurich, Switzerland
[2] ST Ericsson, B-1930 Zaventem, Belgium
[3] ST Ericsson, NL-6534 AB Nijmegen, Netherlands
[4] Catena Wireless Elect, SE-16446 Kista, Sweden
[5] NXP Semicond, NL-6534 AE Nijmegen, Netherlands
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An on-chip protection against IEC 61000-4-2 discharges is presented. The protection level is tested by means of HMM stress. The failure signature is identified by means of TLP testing and physical failure analysis. It is shown that it is possible to accurately predict the HMM failure level by means of a simplified circuit model, calibrated by means of 100ns TLP data.
引用
收藏
页数:8
相关论文
共 50 条
  • [1] On-chip system level protection of FM antenna pin with improved linearity
    Notermans, Guido
    Maksimovic, Dejan
    Vermont, Gerd
    van Maasakkers, Michiel
    Pusa, Fredrik
    Smedes, Theo
    MICROELECTRONICS RELIABILITY, 2011, 51 (12) : 2129 - 2136
  • [2] The Challenges of On-Chip Protection for System level Cable Discharge Events (CDE)
    Lin, Yen-Yi
    Park, Jae
    Isachar, Ori
    Chaikin, Shlomy
    Chundru, Ram
    Duvvury, Charvaka
    Marum, Steve
    Diep, Tom
    ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 2008, 2008, : 125 - +
  • [3] System-level ESD protection design with on-chip transient detection circuit
    Yen, Cheng-Cheng
    Ker, Ming-Dou
    Shih, Pi-Chia
    2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, : 616 - 619
  • [4] Layout optimization of GGISCR structure for on-chip system level ESD protection applications
    Zeng, Jie
    Dong, Shurong
    Wong, Hei
    Hu, Tao
    Li, Xiang
    SOLID-STATE ELECTRONICS, 2016, 126 : 152 - 157
  • [5] On-chip protection
    Chaine, M
    Duvvury, C
    Maloney, T
    Polgreen, T
    Voldman, S
    ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, 1998, : 383 - 383
  • [6] On-chip protection
    Chaine, M
    ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 1998, 1998, : 383 - 383
  • [7] On-chip protection
    Maloney, TJ
    ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS 1997, 1997, : 422 - 422
  • [8] On-chip transient detection circuit for system-level ESD protection in CMOS ICs
    Ker, Ming-Dou
    Yen, Cheng-Cheng
    Shih, Pi-Chia
    PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, : 361 - 364
  • [9] System-Level Access to On-Chip Instruments
    Larsson, Erik
    Gangaraju, Shashi Kiran
    Murali, Prathamesh
    2021 IEEE EUROPEAN TEST SYMPOSIUM (ETS 2021), 2021,
  • [10] On-Chip Antenna for Implantable Applications
    Xu, Li-Jie
    Guo, Yong-Xin
    Wu, Wen
    2013 CROSS STRAIT QUAD-REGIONAL RADIO SCIENCE AND WIRELESS TECHNOLOGY CONFERENCE (CSQRWC), 2013, : 179 - 182