Scaling Trends of Single-Photon Avalanche Diode Arrays in Nanometer CMOS Technology

被引：0
|
作者：
Richardson, Justin A. [1 ,2 ]
Webster, Eric A. G. [1 ]
Grant, Lindsay A. [3 ]
Henderson, Robert K. [1 ]
机构：
[1] Univ Edinburgh, Inst Micro & Nano Syst, Kings Bldg, Edinburgh EH8 9YL, Midlothian, Scotland
[2] Dialog Semicond Ltd, Edinburgh, Midlothian, Scotland
[3] ST Microelect R&D Ltd, Imaging Div, Edinburgh, Midlothian, Scotland
来源：
ADVANCED PHOTON COUNTING TECHNIQUES V | 2011年 / 8033卷
关键词：
single photon avalanche diode; CMOS image sensors; CMOS integrated circuits; DETECTOR;
D O I：
10.1117/12.884097
中图分类号：
O43 [光学];
学科分类号：
070207 ; 0803 ;
摘要：
A family of scaleable single photon avalanche diode (SPAD) structures in 130nm and 90nm CMOS is presented. Performance trends such as dark count rate (DCR), jitter and breakdown voltage are studied versus active diameter for devices ranging from 32 mu m down to 2 mu m. To address pixel pitch we introduce a shared buried n-well approach allowing compact arrays containing both NMOS-transistor readout circuitry and SPAD devices. A pixel pitch of 5 mu m has been achieved in 90nm CMOS technology, offering the potential for future megapixel single photon image sensors.
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页数：8
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