A 32.2-GHz Full Adder in InP DHBT Technology

被引：0
|
作者：
Zhang, Yi [1 ,2 ,3 ]
Li, Xiaopeng [1 ,4 ]
Zhang, Youtao [1 ,4 ]
Zhang, Ying [1 ]
Guo, Yufeng [1 ]
Liu, Zhonghua [3 ]
Gao, Hao [5 ]
机构：
[1] Natl & Local Joint Engn Lab RF Integrat & Microas, Nanjing 210023, Peoples R China
[2] State Key Lab Millimeter Waves, Nanjing 210096, Peoples R China
[3] JiangSu HengXin Technol Co Ltd, Yixing 214222, Peoples R China
[4] Nanjing GuoBo Elect Co Ltd, Nanjing 210016, Peoples R China
[5] Eindhoven Univ Technol, POB 513, NL-5600 MB Eindhoven, Netherlands
来源：
2019 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT2019) | 2019年
基金：
中国博士后科学基金;
关键词：
CLOCK FREQUENCY; ACCUMULATOR;
D O I：
10.1109/rfit.2019.8929166
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology is presented. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce the power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350mW.
引用
收藏
页数：3
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