A novel approach for high-level power modeling of sequential circuits using recurrent neural networks

被引:0
|
作者
Hsieh, WT [1 ]
Shiue, CC [1 ]
Liu, CNJ [1 ]
机构
[1] Natl Cent Univ, Dept Elect Engn, Taoyuan, Taiwan
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, we propose a novel power model for CMOS sequential circuits by using recurrent neural networks (RNN) to learn the relationship between input/output signal statistics and the corresponding power dissipation. The complexity of our neural power model has almost no relationship with circuit size and the numbers of inputs, outputs and flip-flops such that this power model can be kept very small even for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the nonlinear characteristic of power distributions and the temporal correlation of the input sequences. The experimental results have shown that the estimations are still accurate with smaller variation even for short sequences. It implies that our power model can be used in various applications.
引用
收藏
页码:3591 / 3594
页数:4
相关论文
共 50 条
  • [1] A tableless approach for high-level power modeling using neural networks
    Hsu, Chih-Yang
    Hsieh, Wen-Tsan
    Liu, Chien-Nan Jimmy
    Jou, Jing-Yang
    JOURNAL OF INFORMATION SCIENCE AND ENGINEERING, 2007, 23 (01) : 71 - 90
  • [2] Efficient power modelling approach of sequential circuits using recurrent neural networks
    Hsieh, WT
    Shiue, CC
    Liu, CNJ
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2006, 153 (02): : 78 - 86
  • [3] Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach
    Alizadeh, Bijan
    Fujita, Masahiro
    2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 420 - 425
  • [4] High-level automatic pipelining for sequential circuits
    Marinescu, MCV
    Rinard, M
    ISSS'01: 14TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS, 2001, : 215 - 220
  • [5] Neural network macromodel for high-level power estimation of CMOS circuits
    Qiang, W
    Cao, Y
    Yan, YY
    Gao, X
    PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON NEURAL NETWORKS AND BRAIN, VOLS 1-3, 2005, : 1009 - 1014
  • [6] Analytical model for high level power modeling of combinational and sequential circuits
    Gupta, S
    Najm, FN
    IEEE ALESSANDRO VOLTA MEMORIAL WORKSHOP ON LOW-POWER DESIGN, PROCEEDINGS, 1999, : 164 - 172
  • [7] Sequential recurrent neural networks for language modeling
    Oualil, Youssef
    Greenberg, Clayton
    Singh, Mittul
    Klakow, Dietrich
    17TH ANNUAL CONFERENCE OF THE INTERNATIONAL SPEECH COMMUNICATION ASSOCIATION (INTERSPEECH 2016), VOLS 1-5: UNDERSTANDING SPEECH PROCESSING IN HUMANS AND MACHINES, 2016, : 3509 - 3513
  • [8] Intrusion Detection and Classification of Attacks in High-Level Network Protocols Using Recurrent Neural Networks
    Alarcon-Aquino, Vicente
    Oropeza-Clavel, Carlos A.
    Rodriguez-Asomoza, Jorge
    Starostenko, Oleg
    Rosas-Romero, Roberto
    NOVEL ALGORITHMS AND TECHNIQUES IN TELECOMMUNICATIONS AND NETWORKING, 2010, : 129 - 134
  • [9] A Hybrid Power Modeling Approach to Enhance High-Level Power Models
    Nocua, Alejandro
    Virazel, Arnaud
    Bosio, Alberto
    Girard, Patrick
    Chevalier, Cyril
    2016 IEEE 19TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2016, : 151 - 156
  • [10] A Recurrent Neural Networks Based Modeling Approach for Internal Circuits of Electronic Devices
    Zhang Aimin
    Zhang Hang
    Li Hong
    Chen Degui
    2009 20TH INTERNATIONAL ZURICH SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, 2009, : 357 - +