A VLSI architecture for lifting-based wavelet transform with power efficient

In this paper, an efficient VLSI architecture for biorthogonal 9/7 wavelet transform by lifting scheme is presented. The proposed architecture has many advantages including, symmetrical forward and inverse wavelet transform as a result of adopting pipeline parallel technique, as well as area and power efficient because of the decrease in the amount of memory required together with the reduction in the number of read/write accesses on account of using embedded boundary data-extension technique. We have developed a behavioral Verilog HDL model of the proposed architecture, which simulation results match exactly that of the Matlab code simulations. The design has been synthesized into XILINX xcv50e-cs 144-8, and the estimated frequency is 100MHz.