Design and Implementation of A Modified High Performance and Low Power CIC Interpolation Filter

This paper presents a modified cascaded integral comb (CIC) interpolation filter in order to improve filter characteristics and reduce power consumption at the same time. The modified CIC interpolation filter is a two-stage multiplier-less CIC-based interpolator. The first stage is a cascaded CIC filter whereas the second stage is a cascaded CIC filter and a second-order compensator. In an effort to reduce power consumption, the poly-phase decomposition and no-recursive algorithm is used when the modified filter is implemented. Simulation and synthesis results indicate that the stop-band attenuation is up to 137.7 dB and the pass-band drop is only 0.0003 dB with the filter interpolation factor 16. Working at 50 MHz clock frequency, the filter can reduce the power consumption of 16.78%. This new interpolator is implemented on Altera Cyclone III EP3C10E144C8 FPGA.