An Integrated Low-Noise Sensing Circuit With Efficient Bias Stabilization for CMOS MEMS Capacitive Accelerometers

A sensing circuit in 0.35 mu m CMOS technology for CMOS MEMS capacitive accelerometers has been designed in this work with emphasis on managing noise, sensor offset, and the dc bias at input terminals. The issue of dc bias is particularly addressed and an efficient method is proposed. An example of integrating surface micromachined sensors and the designed sensing circuits on the same chip is demonstrated. Experimental results showed that the proposed circuit led to good noise performance, the random offset in the sensors was efficiently compensated, and the input dc bias voltage was well maintained. The sensitivity of the accelerometer is 457 mV/g. The output noise floor is 54 mu g/root Hz, which corresponds to an effective capacitance noise floor of 0.0162 aF/root Hz. The total area of the dual-axis surface micromachined accelerometer chip is 5.66 mm(2) and the current consumption is 1.56 mA under a 3.3 V voltage supply.