Performance Investigation of Source Delta-Doped Vertical Nanowire TFET

In this paper, a source delta-doped vertical nanowire tunnel field-effect transistor is proposed, and its 2D simulations using the Silvaco ATLAS TCAD tool for ultralow-power applications are investigated. Because electron tunneling occurs in a direction parallel to the electric field at the source/channel interface, the ON-state current is higher. By incorporating a delta-doped layer in the source area, the OFF-state leakage current is further reduced. For various electrical parameters, the effects of changing the position of the delta-doped layer is investigated, as well as the effect of changing the doping concentration of the delta-doped layer and the device gate work function. It was possible to achieve a very high current ratio (I-ON/I-OFF) of order similar to 10(11) (with I-ON value 1.52 x 10(-5) A/mu m) with a very low average subthreshold slope of 18 mV/decade, and threshold voltage (V-TH) of 0.57 V.