Compact Implementation of CHAM Block Cipher on Low-End Microcontrollers

In this paper, we presented an optimized implementation of CHAM block cipher on low-end microcontrollers. In order to accelerate the performance of the CHAM block cipher, the architecture of CHAM block cipher and the full specification of 8-bit AVR microcontrollers are efficiently utilized. First, the counter mode of operation for CHAM block cipher is optimized. A number of computations for round function are replaced to look-up table accesses. Second, multiple blocks of CHAM block cipher are computed in a parallel way for high throughput. With the parallel computation, we also presented the adopted encryption. This approach is efficient for long-length data handling. Third, the state-of-art engineering technique is fully utilized in terms of instruction level and register level. The partially unrolled 8-round based implementation is adopted, which avoids a number of word-wise rotation operations. With above optimization techniques, proposed CHAM implementations for counter mode of operation outperform the state-of-art implementations by 30.1%, 9.3%, and 10.0% for CHAM-64/128, CHAM-128/128, and CHAM-128/256, respectively.