Elimination of Common-Mode Voltages Based on Modified SVPWM in Five-Level ANPC Inverters

被引：56
|
作者：
Quoc Anh Le [2 ]
Lee, Dong-Choon [1 ]
机构：
[1] Yeungnam Univ, Dept Elect Engn, Gyongsan 38541, South Korea
[2] Can Tho Univ, Coll Technol, Dept Elect Engn, Can Tho 92000, Vietnam
来源：
IEEE TRANSACTIONS ON POWER ELECTRONICS | 2019年 / 34卷 / 01期
基金：
新加坡国家研究基金会;
关键词：
Active neutral-point clamped (ANPC) inverter; capacitor voltage control; common-mode voltage (CMV); pulsewidth modulation (PWM) inverter; space vector modulation; MOTOR BEARING CURRENTS; CLAMPED INVERTER; MODULATION SCHEMES; REDUCTION; CIRCUIT; DRIVE;
D O I：
10.1109/TPEL.2018.2825230
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and low dv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results.
引用
收藏
页码：173 / 183
页数：11
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