Utilizing Shared Memory Multi-cores to Speed-up the ATPG process

被引:0
|
作者
Hadjitheophanous, Stavros [1 ]
Neophytou, Stelios N. [2 ]
Michael, Maria K. [1 ]
机构
[1] Univ Cyprus, KIOS Res Ctr, CY-1678 Nicosia, Cyprus
[2] Univ Nicosia, KIOS Res Ctr, Nicosia, Cyprus
关键词
ATPG; Parallel Processing; Multi-core systems;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A new test generation methodology is proposed that takes advantage of shared memory multi-core systems. Appropriate parallelization of the main steps of ATPG allocates resources in order to minimize workload duplication and multi-threading race contention, often encountered in parallel implementations. The proposed approach ensures that the obtained acceleration grows linearly with the number of processing cores and, at the same time, keeps the test set size close to that obtained by serial ATPG. The experimental results demonstrate that the proposed methodology achieves higher degree of speed-up than comparable state-of-the-art multi-core based tools, while maintains similar test set sizes.
引用
收藏
页数:6
相关论文
共 50 条
  • [1] Redundant Execution on Heterogeneous Multi-cores Utilizing Transactional Memory
    Amslinger, Rico
    Weis, Sebastian
    Piatka, Christian
    Haas, Florian
    Ungerer, Theo
    [J]. ARCHITECTURE OF COMPUTING SYSTEMS, 2018, 10793 : 155 - 167
  • [2] Architectural support for efficient message passing on shared memory multi-cores
    Titos-Gil, Ruben
    Palomar, Oscar
    Unsal, Osman
    Cristal, Adrian
    [J]. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2016, 95 : 92 - 106
  • [3] DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores
    Titos-Gil, Ruben
    Palomar, Oscar
    Unsal, Osman
    Cristal, Adrian
    [J]. 2015 44TH INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING (ICPP), 2015, : 130 - 139
  • [4] Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on-Chip
    Meng, Hongyu
    Wang, Donglin
    Liu, Zijun
    Guo, Yang
    [J]. 2018 8TH INTERNATIONAL CONFERENCE ON ELECTRONICS INFORMATION AND EMERGENCY COMMUNICATION (ICEIEC), 2018, : 71 - 74
  • [5] Exploring locking & partitioning for predictable shared caches on multi-cores
    Suhendra, Vivy
    Mitra, Tulika
    [J]. 2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 300 - 303
  • [6] Peformance Optimization Utilizing Heterogeneous Multi-cores for Smart TV Applications
    Lee, Taeyoung
    Ann, Wooram
    Hahm, Cheulhee
    [J]. 18TH IEEE INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE 2014), 2014,
  • [7] Multicast routing protocol using multi-cores unidirectional shared trees
    [J]. Ma, Y.-L., 2001, Science Press (24):
  • [8] Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
    Li, Yan
    Suhendra, Vivy
    Liang, Yun
    Mitra, Tulika
    Roychoudhury, Abhik
    [J]. 2009 30TH IEEE REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, 2009, : 57 - 67
  • [9] Timing analysis of concurrent programs running on shared cache multi-cores
    Liang, Yun
    Ding, Huping
    Mitra, Tulika
    Roychoudhury, Abhik
    Li, Yan
    Suhendra, Vivy
    [J]. REAL-TIME SYSTEMS, 2012, 48 (06) : 638 - 680
  • [10] Timing analysis of concurrent programs running on shared cache multi-cores
    Yun Liang
    Huping Ding
    Tulika Mitra
    Abhik Roychoudhury
    Yan Li
    Vivy Suhendra
    [J]. Real-Time Systems, 2012, 48 : 638 - 680