共 50 条
- [1] Redundant Execution on Heterogeneous Multi-cores Utilizing Transactional Memory [J]. ARCHITECTURE OF COMPUTING SYSTEMS, 2018, 10793 : 155 - 167
- [3] DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores [J]. 2015 44TH INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING (ICPP), 2015, : 130 - 139
- [4] Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on-Chip [J]. 2018 8TH INTERNATIONAL CONFERENCE ON ELECTRONICS INFORMATION AND EMERGENCY COMMUNICATION (ICEIEC), 2018, : 71 - 74
- [5] Exploring locking & partitioning for predictable shared caches on multi-cores [J]. 2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 300 - 303
- [6] Peformance Optimization Utilizing Heterogeneous Multi-cores for Smart TV Applications [J]. 18TH IEEE INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE 2014), 2014,
- [7] Multicast routing protocol using multi-cores unidirectional shared trees [J]. Ma, Y.-L., 2001, Science Press (24):
- [8] Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores [J]. 2009 30TH IEEE REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, 2009, : 57 - 67
- [10] Timing analysis of concurrent programs running on shared cache multi-cores [J]. Real-Time Systems, 2012, 48 : 638 - 680