Characterization and Reliability Assessment of Solder Microbumps and Assembly for 3D IC Integration

In this investigation, Cu/Sn lead-free solder microbumps with 10 mu m pads on 20 mu m pitch are designed and fabricated. The chip size is 5mm x 5mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. With the current process, the undercut is less than 1 mu m and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder micro bumped chip is bonded on a Si wafer (chip-to-wafer or C2W bonding). Furthermore, the micro-gap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips w/o underfill is measured and exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs are evaluated by reliability tests, including thermal cycling test (-55 reversible arrow 125 degrees C, dwell and ramp times = 15 min). Finally, ultra find-pitch (5 mu m pads on 10 mu m pitch) lead-free solder microbumping is explored.