C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

被引:1
|
作者
Onojima, Norio [1 ]
Kasamatsu, Akihumi [1 ]
Hirose, Nobumitsu [1 ]
Mimura, Takashi [1 ,2 ]
Matsui, Toshiaki [1 ]
机构
[1] Natl Inst Informat & Commun Technol NICT, Koganei, Tokyo 1848795, Japan
[2] Fujitsu Labs Ltd, Atsugi, Kanagawa 2430197, Japan
关键词
iGe; HEMT; MIS; C-V;
D O I
10.1016/j.apsusc.2008.02.147
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
Electrical properties of Schottky-and metal -insulator -semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance -voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky-and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (gm) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency fT compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel. (C) 2008 Elsevier B. V. All rights reserved.
引用
收藏
页码:6162 / 6164
页数:3
相关论文
共 50 条
  • [1] On the C-V characteristics of nanoscale strained gate-all-around Si/SiGe MOSFETs
    Kumari, Amrita
    Kumar, Subindu
    Sharma, Tarun Kumar
    Das, Mukul K.
    SOLID-STATE ELECTRONICS, 2019, 154 : 36 - 42
  • [2] C-V characterization of bonded Si/SiO2/Si structures
    Huang, Qingan
    Chen, Junning
    Zhang, Huizhen
    Tong, Qinyi
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 1994, 15 (05): : 354 - 360
  • [3] Analysis of Abnormal C-V Hump on Si3N4 MIS-HEMT With Mesa Isolation Under Negative Gate Bias Stress
    Lee, Ya-Huan
    Chang, Kai-Chun
    Lin, Hsin-Ni
    Tai, Mao-Chou
    Huang, Wei-Chen
    Lin, Jia-Hong
    Kuo, Hung-Ming
    Lee, Jason
    Huang, I-Yu
    Chang, Ting-Chang
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (04) : 2349 - 2354
  • [4] ANALYSIS OF C-V DATA IN ACCUMULATION REGIME OF MIS STRUCTURES
    LEHOVEC, K
    LIN, ST
    SOLID-STATE ELECTRONICS, 1976, 19 (12) : 993 - 996
  • [5] C-V test structures for metal gate CMOS
    Bankras, Radko G.
    Tiggelman, Mark P. J.
    Negara, M. Adi
    Sasse, Guido T.
    Schmitz, Jurriaan
    ICMTS 2006: PROCEEDINGS OF THE 2006 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2006, : 226 - +
  • [6] FLUCTUATION OF FIXED OXIDE CHARGE IN MIS STRUCTURES AND C-V MEASUREMENTS
    PEIKOV, PC
    DOKLADI NA BOLGARSKATA AKADEMIYA NA NAUKITE, 1973, 26 (10): : 1311 - 1314
  • [7] C-V PROPERTIES OF MIS STRUCTURES WITH A FERROELECTRIC POLYMER INSULATING LAYER
    GUY, I
    ARAFIN, P
    INTEGRATED FERROELECTRICS, 1995, 9 (1-3) : 199 - 205
  • [8] Effect of traps-to-gate tunnel communication on C-V characteristics of MIS capacitors
    Mazurak, A.
    Jasinski, J.
    Majkusiak, B.
    MICROELECTRONIC ENGINEERING, 2019, 215
  • [10] An Analytical Model for the Gate C-V Characteristics of UTB III-V-on-Insulator MIS Structure
    Islam, Muhammad Mainul
    Alam, Md. Nur Kutubul
    Sarker, Md. Shamim
    Islam, Md. Rafiqul
    Haque, Anisul
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2017, 5 (05): : 335 - 339