Built-In Self-Test of Embedded Memory Cores in Virtex-5 Field Programmable Gate Arrays

被引：0

作者：

Dailey, Justin L. ^{[1
]}

Garrison, Brooks R. ^{[1
]}

Pulukuri, Mary D. ^{[1
]}

Stroud, Charles E. ^{[1
]}

机构：

[1] Auburn Univ, Dept Elect & Comp Engn, Auburn, AL 36849 USA

来源：

PROCEEDINGS SSST 2011: 43RD IEEE SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper introduces and details a Built-In Self-Test (BIST) approach designed for the embedded Block Random Access Memories (BRAMs) found within Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). The BIST is designed to test the BRAMs in all configurable modes of operation including single-port, dual-port, first-in first-out (FIFO), first-in first-out with error correcting code (FIFOECC), and error correcting code (ECC) modes. The BIST architecture and implementation in actual Virtex-5 FPGAs will be discussed along with fault detection and timing analysis data taken from those implementations.

引用

页码：220 / 225

页数：6

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