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- [1] Designs for reducing test time of distributed small embedded SRAMs 19TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2004, : 120 - 128
- [3] Test/Repair area overhead reduction for small embedded SRAMs PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 37 - +
- [4] Integrated Read Assist-Sense Amplifier Scheme for High Performance Embedded SRAMs 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 137 - 140
- [5] A Multiword Based High Speed ECC Scheme for Low-voltage Embedded SRAMs ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2008, : 226 - 229
- [6] Reducing test time of embedded SRAMs RECORDS OF THE 2003 INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING, 2003, : 47 - 52
- [7] IDDT testing of embedded CMOS SRAMs DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, : 1117 - 1117
- [8] iDDT testing of CMOS embedded SRAMs 6TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XVII, PROCEEDINGS: INDUSTRIAL SYSTEMS AND ENGINEERING III, 2002, : 545 - 550
- [9] BIST for embedded SRAMs in system on chips ESA '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS AND APPLICATIONS, 2005, : 74 - 80
- [10] Crossbar Sector Addressing Scheme on SRAMs 2017 4TH PANHELLENIC CONFERENCE ON ELECTRONICS AND TELECOMMUNICATIONS (PACET), 2017, : 49 - 52