IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDA

被引:1
|
作者
Jung, Jinwook [1 ]
Kahng, Andrew B. [2 ]
Varadarajan, Ravi [2 ]
Wang, Zhiang [2 ]
机构
[1] IBM Res, Yorktown Hts, NY 10598 USA
[2] Univ Calif San Diego, La Jolla, CA USA
关键词
VLSI CAD; open source; EDA; machine learning;
D O I
10.1145/3508352.3561379
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper describes new elements in the RDF-2022 release of the DATC Robust Design Flow, along with other activities of the IEEE CEDA DATC. The RosettaStone initiated with RDF-2021 has been augmented to include 35 benchmarks and four open-source technologies (ASAP7, NanGate45 and SkyWater130HS/HD), plus timingsensible versions created using path-cutting. The Hier-RTLMP macro placer is now part of DATC RDF, enabling macro placement for large modern designs with hundreds of macros. To establish a clear baseline for macro placers, new open-source benchmark suites on open PDKs, with corresponding flows for fully reproducible results, are provided. METRICS2.1 infrastructure in OpenROAD and OpenROAD-flow-scripts now uses native JSON metrics reporting, which is more robust and general than the previous Python scriptbased method. Calibrations on open enablements have also seen notable updates in the RDF. Finally, we also describe an approach to establishing a generic, cloud-native large-scale design of experiments for ML-enabled EDA. Our paper closes with future research directions related to DATC's efforts.
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页数:8
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