Performance Comparison of Adder Architectures on 28nm FPGA

Adders are one of the most desirable entities in processor data path architecture. Since long, VLSI engineers are working towards optimization and miniaturization of adder architectures to ultimately improve the performance of processors. As the technology is scaling down, challenges towards optimization are also increasing. In this paper we present the implementation of various 16 bit adder architectures including parallel prefix adders and their comparative analysis based on ultimate performance parameters-area and power at 28nm technology. All designs have been synthesized and implemented on Xilinx Zynq-7000 FPGA board using Xilinx Vivado 14.4 design tool. Verilog HDL is used as programming HDL. Weinberger adder provides the best area solution.