Low-Noise High-Speed CMOS CID Readout IC

This paper presents a design technique of low-noise and high-speed CMOS readout IC for large-area charge integrating detectors. In conventional structures, the readout speed is inevitably reduced to improve the noise rejection performance due to an RC low-pass filter at output. To alleviate the trade-off relationship between the speed and SNR, the response approximation scheme is proposed in this paper. It employs a multi-sampling technique for accurate extraction of RC delay response. The readout circuit is designed for a 0.18-mu m CMOS technology, and achieves an input-referred noise of 561 e(-) rms and 1-row readout time of 21 mu s. The reconstructed output response has an accuracy of 14-bit by utilizing only 1-tau sampling time.