FPGA Based Control and Data Acquisition Interfaces for PANDA Components

For the upcoming PANDA detector at FAIR (Darmstadt, Germany), various components for timing distribution, control and data acquisition are being constructed. Design objective is to support testing of detector components in a laboratory environment, while keeping it scalable and use hardware platforms and interfaces already agreed on for the final implementation. For timing and certain control tasks, the "SODANET" protocol is used which is developed with other contributors in the PANDA project. The protocol runs on fast serial links which are part of modern FPGAs; the links are operated in a synchonous mode so that the timimg accuracy is defined by the link clock. For data transfer, the CERN "GBT" platform is used which is a unidirectional link with Forward Error Correction. As hardware platform, MicroTCA. 4 is used; a suitable AMC module has been developed by DESY and KIT.