Chip package interaction evaluation for a high performance 65nm and 45nm CMOS Technology in a stacked die package with C4 and wirebond interconnections

被引：3

作者：

Muzzy, Christopher ^{[1
]}

Danovitch, David ^{[1
]}

Gagnon, Hugues ^{[1
]}

Hannon, Robert ^{[1
]}

Kinser, Emily ^{[1
]}

McLaughlin, Paul V. ^{[1
]}

Mongeau, Guy ^{[1
]}

Quintal, Jean-Guy ^{[1
]}

Sylvestre, Jocelyn ^{[1
]}

Turcotte, Eric ^{[1
]}

Wright, Judith ^{[1
]}

机构：

[1] IBM Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA

来源：

58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/ECTC.2008.4550170

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

An evaluation of 65nm and 45nm CMOS Technology in a stacked die package is presented. The technology uses SiCOH advanced low K and ultra low K back end of line (BEOL) for high performance. A BEOL specific test vehicle was fabricated in these technologies and both flip chip and wirebond die used in a stacked die configuration. Manufacturability evaluations for bond and assembly processes and materials were performed and reliability studies completed on assembled modules. Results will show that the technologies are reliable in this packaging configuration.

引用

页码：1472 / 1475

页数：4

共 31 条

[1] Chip package interaction for 65nm CMOS technology with C4 interconnections
Farooq, Mukta
Melville, Ian
Muzzy, Christopher
McLaughlin, Paul V.
Hannon, Robert
Sauter, Wolfgang
Muncy, Jennifer
Questad, David
Carey, Charles
Cullinan-Scholl, Mary
McGahay, Vincent
Angyal, Matthew
Nye, Henry
Lane, Michael
Liu, Xiao Hu
Shaw, Thomas
Murray, Conal
PROCEEDINGS OF THE IEEE 2007 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2007, : 196 - +
[2] Chip package interaction results & Modeling for 65nm CMOS BEOL with c4 interconnections
Farooq, Mukta
Melville, Ian
Muzzy, Christopher
McLaughlin, Paul V.
Hannon, Robert
Ferguson, Craig
Dubuque, Rachel
Sauter, Wolfgang
Muncy, Jennifer
Questad, David
Carey, Charles
Cullinan-Scholl, Mary
McGahay, Vincent
Angyal, Matthew
Nye, Henry
Lane, Michael
Liu, Xiao Hu
Shaw, Thomas
Murray, Conal
ADVANCED METALLIZATION CONFERENCE 2007 (AMC 2007), 2008, 23 : 631 - 637
[3] Improvement of interfacial adhesion in chip-package interaction of 65nm node SoC
Kitsutaka, H
Suzuki, K
Inoto, H
Kawakami, M
Honda, K
Hasunuma, M
Ito, S
Miyajima, H
Fujita, K
Kaneko, H
Yoda, T
Oyamatsu, H
Yamada, S
Matsuoka, F
Noguchi, T
ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004), 2004, : 265 - 268
[4] Technology portable, 0.04mm2, Ghz-rate ΣΔ modulators in 65nm and 45nm CMOS
van Veldhoven, Robert H. M.
Nizza, Nicolo
Breems, Lucien J.
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : 72 - 73
[5] Chip/Package design and technology trade-offs in the 65nm cell broadband engine
Harvey, P.
Zhou, Y.
Yamada, G.
Kawasaki, K.
Questad, D.
Lafontant, G.
Mandrekar, R.
Suminaga, S.
Yamaji, Y.
Noma, H.
Nishio, T.
Mori, H.
Tamura, T.
Yazawa, K.
Takiguchi, I.
Obde, T.
White, R.
Malhotra, A.
Audet, J.
Wakil, J.
Sauter, W.
Hosomi, E.
57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS, 2007, : 27 - +
[6] High performance 30nm bulk CMOS for 65nm technology node(CMOS5)
Morifuji, E
Kanda, M
Yanagiya, N
Matsuda, S
Inaba, S
Okano, K
Takahashi, K
Nishigori, M
Tsuno, H
Yamamoto, T
Hiyama, K
Takayanagi, M
Oyamatsu, H
Yamada, S
Noguchi, T
Kakumu, M
INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 655 - 658
[7] Reliability of high-end flip-chip package with large 45nm ultra low-k die
Bansal, Anurag
Kang, Teck-Gyu
Li, Yuan
58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 1357 - 1361
[8] High Performance Digital to Analog Converter Using CMOS 45nm Technology
Raju, David Solomon Y.
Shyamala, K.
Sumalatha, Ch
Sunilkumar, J.
PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES (ICICT 2021), 2021, : 357 - 361
[9] Investigation of ESD Performance of Silicide-Blocked Stacked NMOSFETs in a 45nm Bulk CMOS Technology
Chatty, K.
Alvarez, D.
Abou-Khalil, M. J.
Russ, C.
Li, J.
Gauthier, R.
ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 2008, 2008, : 304 - +
[10] High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
Luo, Z.
Rovedo, N.
Ong, S.
Phoong, B.
Eller, M.
Utomo, H.
Ryou, C.
Wang, H.
Stierstorfer, R.
Clevenger, L.
Kim, S.
Toomey, J.
Sciacca, D.
Li, J.
Wille, W.
Zhaol, L.
Teo, L.
Dyer, T.
Fang, S.
Yan, J.
Kwon, O.
Kwon, O.
Park, D.
Holt, J.
Han, J.
Chan, V.
Yuan, J.
Kebede, T.
Lee, H.
Kim, S.
Lee, S.
Vayshenker, A.
Yang, Z.
Tian, C.
Ng, H.
Shang, H.
Hierlemann, M.
Ku, J.
Sudijonol, J.
Ieong, M.
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 16 - +

← 1 2 3 4 →