DFM-aware CAD design flow for SiP foundry business and applications

It is well understood that the advanced SiP (system-in-package) is considered as practical "structural scaling" approaches with mature-nodes semiconductor, in additional to the expensive "lithographic scaling" with high capital investments for SOC (system-on-chip). Among millimeter(mm)-scale PCB flows and micrometer(um)-scale chip designs, SiP topics in the mm-to-um range becomes the new battlefield for EDAs from IC and PCB players. However, each side may have its legacy issues or domain constraints, and hesitate in more resources for decent design-technology collaboration, so called DFM (design-for-manufacturing) or MFD (manufacturing-for design) while the advanced SiP manufacturers or specialty foundries and designers are all expecting better ecosystem and solutions. Such heterogenous domains integration triggers new challenges in either smooth database handling, SiP design/CAD methodologies, and mask tooling/manufacturing flows. Referencing what have been done in advanced IC technologies, this article has studied and summarized some gap-closure approaches about SiP design/CAD methodologies.