Refinement of the subthreshold slope modeling for advanced bulk CMOS devices

We present here a simple analytical model of the subthreshold slope of CMOS devices that successfully describes the long-channel plateau, the initial improvement for medium gate lengths, and the final degradation for short gate lengths. The model is based on the voltage-doping transformation (VDT) that leads to a new term in the subthreshold slope expression, explaining the degradation of the slope at very short channels. The potential minimum at the virtual cathode was expressed using a semiempirical expression that allows our model to fit to data that were extracted from simulation in a wide range of device parameters. Finally, the new slope model successfully reproduced experimental data that were measured on devices based on 90- and 65-nm technologies, demonstrating the validity of our model for advanced bulk CMOS technologies.