Process Challenges for Integration of Copper Interconnects with Low-k Dielectrics

Copper interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability compared to Al interconnects. Initially SiO2 was used as the interlevel dielectric. To reduce interconnect capacitance, C-doped SiO2 or SiCOH was introduced at the 90 nm node, and porous SiCOH was introduced at the 45 nm node, to achieve a dielectric constant of 2.5 or less. However, there are many process problems with the integration of Cu interconnects and porous low-k dielectrics, including patterning, liner coverage, chemical mechanical polishing (CMP), and packaging. In this paper, some of the key integration challenges are discussed.