A Deep Neural Network Accelerator Based on Tiled RRAM Architecture

被引：54
|
作者：
Wang, Qiwen [1 ]
Wang, Xinxin [1 ]
Lee, Seung Hwan [1 ]
Meng, Fan-Hsuan [1 ]
Lu, Wei D. [1 ]
机构：
[1] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA
来源：
2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年
关键词：
D O I：
10.1109/iedm19573.2019.8993641
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
State-of-the-art deep neural networks (DNNs) have been successfully mapped on an RRAM-based tiled in-memory computing (IMC) architecture. Effects of moderate array size and quantized partial products (PPs) due to ADC precision constraints have been analyzed. Methods were developed to solve these challenges and preserve DNN accuracies and IMC performance gains in the tiled architecture. Popular models including VGG-16 and MobileNet have been successfully implemented and tested on ImageNet dataset.
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页数：4
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