The influence of "off-axis" from {100} oriented Si wafers on junction depth and sheet resistance for low-energy implantation and rapid thermal annealing

According to the recently released 1999 National Technology Roadmap for Semiconductors, the S/D extension junction will be in the range of a few tens of nanometers for the upcoming 180 nm and 130 nm nodes. Although the junctions have to become shallower, a decreasing sheet resistance is required. The formation of ultra-shallow junctions is mainly influenced by three important parameters, these are: dose and energy control during ion implantation, a controlled gaseous ambient during RTA (rapid thermal anneal), and a controlled and reproducible thermal budget during RTA. The requirements for production tools have become progressively more stringent, but the crystal off-orientation of the wafer surface condition as an issue in reproducible USJ formation has been-neglected. In Si wafer production, the exact {100} orientation of the wafer surface is determined by the ingot sawing accuracy and typically done with a tolerance of +/-0.1 degrees Prior to this experiment, however, the influence of such a variance in the wafer off-orientations on the junction characteristics had not been investigated. For our experiments repeatable "off-axis" from {100} sliced 200 mm silicon wafers were implanted with B-11(+), As-75(+) or P-31(+) at a tilt and twist angle of 0 degrees to investigate the effects on junction depth and sheet resistance. The acceleration voltage varied between 500 eV (B-11(+)) and 5 keV (As-75(+)). The off-orientation varied between exact 0 degrees and the channeling-reduction-angle for boron of 7.0 degrees (e.g. 0.35 degrees, 1.0 degrees, 4.0 degrees). Species depending data of as-implanted distributions as well as soak time (1050 degreesC 10 s) and flash annealed (with a ramp rate of 350 K/s) wafers are presented and the influences of the off-oriented sliced wafers on junction depth and sheet resistance are discussed.