Hardware/software cost analysis of interrupt processing strategies

被引：1
|
作者：
Samadzadeh, MH [1 ]
Garalnabi, LE [1 ]
机构：
[1] Oklahoma State Univ, Stillwater, OK 74078 USA
来源：
IEEE MICRO | 2001年 / 21卷 / 03期
关键词：
D O I：
10.1109/40.928766
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new study compares the architectural design and implementation costs of five strategies that let pipelined processors support precise interrupts. Hardware dominates the cost of all strategies except checkpoint repair, which, depending on the implementation, can incur either high software or hardware costs.
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页码：69 / 76
页数：8
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