Integrated classifier simulator and neurochip VHDL implementation

被引：0
|
作者：
Efremides, OB
Bekakos, MP [1 ]
Evans, DJ
机构：
[1] Democritus Univ Thrace, Sch Engn, Dept Elect & Comp Engn,Lab Digital Syst, Sect Elect & Informat Syst Technol, Thrace, Greece
[2] Nottingham Trent Univ, Fac Engn & Comp, Dept Comp, Nottingham, England
来源：
INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS | 2003年 / 80卷 / 11期
关键词：
ALN; simulator; VHDL;
D O I：
10.1080/0020716031000148223
中图分类号：
O29 [应用数学];
学科分类号：
070104 ;
摘要：
In this work, the development of a simulator for a system capable of recognizing and classifying patterns into certain classes (families) is investigated. The classification system integrating hardware and software components is presented. The entire system simulator is developed using Java programming language, while its hardware parts are implemented and simulated using VHDL.
引用
收藏
页码：1343 / 1350
页数：8
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