Power Estimation of Modified Booth Recoder for Efficient Add-Multiply Operator

被引:0
|
作者
Shruthilaya, K. [1 ]
Vinoth, M. [1 ]
机构
[1] Chettinad Coll Engn & Technol, Dept ECE, Karur, Tamil Nadu, India
关键词
Modified Booth recoding; Add-Multiply operation and Sum to Modified Booth(S-MB) recoding; HIGH-SPEED; FFT;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
To improve the performance and speed of Digital signal processing operations such as FFT (Fast Fourier Transform), DCT (Discrete Cosine Transform) and FIR (Finite Impulse Response). We can implement the arithmetic operations in a fused manner. By direct recoding of the sum of two numbers in Modified Booth, the Add-Multiply operator have been fused together to reduce the power consumption, hardware complexity and delay. The implementation of different recoding schemes and estimation of the power and delay were done using Microwind Tool.
引用
收藏
页码:1684 / 1689
页数:6
相关论文
共 13 条
  • [1] An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator
    Tsoumanis, Kostas
    Xydis, Sotiris
    Efstathiou, Constantinos
    Moschopoulos, Nikos
    Pekmestzi, Kiamal
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (04) : 1133 - 1143
  • [2] An Efficient Modified Booth Recoder for Different Applications
    Bai, Vadithe Madhu
    Sailaja, M.
    PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND ELECTRONICS SYSTEMS (ICCES), 2016, : 793 - 796
  • [3] Algorithm for designing efficient VLSI concurrent add-multiply and add-multiply-add cells for DSP applications
    Poornaiah, DV
    ELECTRONICS LETTERS, 2000, 36 (05) : 399 - 400
  • [4] Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
    Efstathiou, Constantinos
    Moshopoulos, N.
    Axelos, N.
    Pekmestzi, K.
    INTEGRATION-THE VLSI JOURNAL, 2014, 47 (01) : 140 - 147
  • [5] VLSI Implementation of an efficient Fused Add-Multiply Unit using Constant-time addition
    Durgadevi, S.
    Seshasayanan, R.
    2015 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS), 2015,
  • [6] Characterization of RNS Multiply-Add Units for Power Efficient DSP
    Cardarilli, Gian Carlo
    Nannarelli, Alberto
    Petricca, Massimo
    Re, Marco
    2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2015,
  • [7] Area Efficient Low Power Modified Booth Multiplier for FIR Filter
    Haridas, Greeshma
    George, David Solomon
    INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING, SCIENCE AND TECHNOLOGY (ICETEST - 2015), 2016, 24 : 1163 - 1169
  • [8] Implementation of Low Power and Area Efficient Floating-Point Fused Multiply-Add Unit
    Dhanabal, R.
    Sahoo, Sarat Kumar
    Bharathi, V.
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON SOFT COMPUTING SYSTEMS, ICSCS 2015, VOL 1, 2016, 397 : 329 - 342
  • [9] Optimizing Encoder and Decoder Blocks for a Power-Efficient Radix-4 Modified Booth Multiplier
    Scheunemann, Jean C.
    Sigales, Marlon S.
    Fonseca, Mateus B.
    da Costa, Eduardo A. C.
    34TH SBC/SBMICRO/IEEE/ACM SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2021), 2021,
  • [10] Some modified estimators for efficient estimation of power function model
    Bhatti, Sajjad Haider
    Irfan, Muhammad
    Azeem, Muhammad
    Javed, Maria
    Raza, Muhammad Ali
    QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL, 2024, 40 (01) : 550 - 560