1/f noise in CMOS transistors for analog applications

The present paper focuses on both p- and n-channel MOS transistors for analog applications that are fabricated in a commercial ''low noise process'', have a relatively large area and exhibit long channel behavior. A systematic study of 1/f noise in CMOS transistors is reported under various bias conditions ranging from subthreshold to strong saturation regions of operation. In the present study, in the saturation region, the range of gate and drain bias voltages is limited to values where the decrease in surface mobility is very small and practically negligible. The voltage range corresponding to this assumption is obtained from the measured transconductance. A useful model for analog designers is presented for such large area transistors with a practically constant surface mobility. The measured input-referred noise in strong inversion of such transistors is well modeled with S-VG=M/(C(ox)(2)ZLf(beta)) where M is a process dependent empirical constant, as verified by measurements. The measured values of M for several n-mos and p-mos transistors with different areas and process runs (but exposed to the same ''low noise process'') vary, respectively, between 4+/-2 10(-31) Cb/cm(2) and 2+/-1 10(-32) Cb/cm(2), Below threshold voltage, a significant reduction is observed in the input-referred noise as gate voltage is decreased, corresponding to the prediction of the model and due to the exponential reduction of the inversion capacitance with gate voltage. This behavior is observed for both n-mos and p-mos transistors. From the measurements and modeling it is concluded that to reduce 1/f noise in analog applications it is recommended to design the largest area transistor in the available chip area, to rely on p-channel transistors and to operate in subthreshold. If operation in saturation is required, it is advised to limit the bias voltages to values corresponding to a constant mobility since in p-mos transistors M increases with higher gate voltages.