FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP

Field Programmable Gate Arrays (FPGA) offers a faster, increasingly adjustable arrangement. Earlier Data Encryption Standard (DES) algorithms have been developed, however it could not keep up with advancement in a technology and it is no longer appropriate for security. With this motivation, this work developed an efficient FPGA implementation of Advanced Encryption Standard (AES) targets to investigate a huge number of security processes followed in the TCP/IP protocol suite and to suggest a novel new architecture for the existing version. The first contribution of the studies turned into to provide the safety for packages of the utility layer protocols. The AES cryptographic encryption, decryption and key management set of rules to for the safety of transmission control protocol/internet protocol (TCP/IP) protocol suite turned into carried out. AES is one of the maximum famous cryptographic algorithms used for records safety. The cost and consumption of power in the AES can be decreased substantially by way of optimizing the structure of AES. This research article projects an implementation based on modification in Mix column in AES techniques which gives a compact structure with efficient mix column Boolean expression the usage of resource sharing architecture and gate replacement method. The ON-chip power utilization and area overhead of the proposed hardware implementation outperforms the preceding work performed in this area. The proposed architecture have been carried out on the most latest virtex 6 lower power Field programmable gate array (FPGA), whereas overhead and on-chip utilization of power are compared with the previous works and it is proved that proposed method has lower area utilization and ON-Chip utilization of power. (C) 2019 Elsevier B.V. All rights reserved.