A Comprehensive Scheme for Contention Management in Hardware Transactional Memory

被引:0
|
作者
Wang, Xiaoqun [1 ]
Ji, Zhenzhou [1 ]
Fu, Chen [1 ]
Hu, Mingzeng [1 ]
机构
[1] Harbin Inst Technol, Harbin 150001, Peoples R China
来源
关键词
hardware transactional memory; contention management; parallel programming; multicore processors;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Transactional Memory (TM) is one kind of approach to maximize parallel performance for multicore systems. There are conflicts When two or more parallel transactions access the same location and at least one access is a write. Contention management(CM) refers to the mechanisms used to guarantee forward to avoid performance pathology, and to promote throughput. In this paper, we introduce a new CM police. We remitted six of seven performance pathologies summered by Bobba. Our result shows high performance for large transactions, while get moderate improvement or little slowdown for small transactions. The performance of the systems used this policies combined with other policy are steady.
引用
收藏
页码:397 / 403
页数:7
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