Performance and power impact of issue-width in chip-multiprocessor cores

This paper explores the trade-off between the issue-width of the cores and the number of cores on a chip by considering design points with comparable area with respect to both performance and energy. We focus on scalable parallel applications from SPLASH-2. While they are known to benefit from as many cores as possible we show that these applications can be run as efficiently and with comparable power consumption on a chip-multiprocessor (CMP) with fewer but wider-issue cores. This is attributable to their inherent ILP and the fact that fewer cores result in less performance and power consumption losses in the on-chip memory hierarchy.