Design of fast large fan-in CMOS multiplexers accounting for interconnects

In this paper, the design of high-fan-in CMOS multiplexers based on the heterogeneous-tree approach is discussed. In particular, a strategy to minimize the delay of multiplexers is developed that accounts for the interconnect parasitics from the beginning, thereby extending the previous results introduced in [1] which did not consider the effect of interconnects. The design criteria derived are very simple, and are shown to be strongly affected by the interconnects, as one expects in current Deep-Submicron (DSM) VLSI circuits. It is also shown that neglecting parasitics in the multiplexer optimization can lead to a speed degradation as high as 80%. The results are validated through post-layout simulations on a 90-nm CMOS process.