FPGA-Based, Multi-Processor HW-SW System for Single-Chip Crypto Applications

被引：1

作者：

Fitzgerald, Andrew ^{[1
,2
]}

Lukowiak, Marcin

Kurdziel, Michael ^{[1
,2
]}

Mackey, Christopher ^{[1
,2
]}

Smith, Kenneth, Jr. ^{[1
,2
]}

Boorman, Brian ^{[1
,2
]}

Harris, Duncan ^{[1
,2
]}

Skiba, William ^{[1
,2
]}

机构：

[1] Harris Corp, RF Commun Div, Rochester, NY 14610 USA

[2] Harris Corp, RF Commun Div, Rochester, NY 14610 USA

来源：

MILITARY COMMUNICATIONS CONFERENCE, 2010 (MILCOM 2010) | 2010年

关键词：

HARDWARE ARCHITECTURE; AES; GCM;

D O I：

10.1109/MILCOM.2010.5680127

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses design and analysis of an FPGA-based system containing two isolated, Altera Nios II softcore processors that share data through two custom cryptoengines. FPGA-based Single-Chip Cryptographic (SCC) techniques were employed to ensure full red/black separation. Each crypto-engine is a hardware implementation of the Advanced Encryption Standard (AES), operating in Galois/Counter mode (GCM). The features of the AES crypto-engines were varied with the goal of determining which best achieve high performance or minimal hardware usage. To quantify the costs of red/black separation, a thorough analysis of resource requirements was performed. The hardware/software approach was utilized in order to provide appropriate levels of flexibilty and performance, allowing for a range of target applications.

引用

页码：1317 / 1322

页数：6

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