An accurate HJFET capacitance-voltage model for implementation with a circuit simulator

被引:2
|
作者
Matsuno, N
Yano, H
Hida, H
Maeda, T
机构
[1] Microelectronics Research Laboratories, NEC Corporation
关键词
CAD model; circuit simulation; GaAs; gate capacitance; HJFET;
D O I
10.1109/16.556146
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a new accurate HJFET capacitance model to implement with a circuit simulator, This is an analytical model that describes capacitance-voltage (C-V) characteristics over a wide supply voltage range, The model for a capacitance component due to two-dimensional electron gas (2-DEG) conduction is based on gradual channel approximation, and takes into account the gradual capacitance transition near the threshold voltage, It also takes into account the held dependence of the 2-DEG mobility, which is very strong for deep sub-micron devices, The model for parasitic MESFET capacitance is based on the formula for a Schottky diode, Since the model consists of physical parameters, it provides feedback between the fabrication process and circuit design, The simulated results agree well with the measurements.
引用
收藏
页码:373 / 378
页数:6
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