Predicting performance potential of modern DSPs

被引：3
|
作者：
Ghazal, N [1 ]
Newton, R [1 ]
Rabaey, J [1 ]
机构：
[1] Univ Calif Berkeley, Dept EECS, Berkeley, CA 94720 USA
来源：
37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000 | 2000年
关键词：
D O I：
10.1145/337292.337431
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
High-level development tools for digital signal processors(DSPs) remain unable to extract optimal performance from them without the designer's in-depth knowledge of the architecture. In this paper we describe our approach to Retargetable Estimation and show how and why it can be effective in quickly predicting and guiding toward hand-optimized performance of modems DSPs for a given application described in a high-level language. We also contrast the advantages of this scheme with those of a full-featured optimizing compiler.
引用
收藏
页码：332 / 335
页数：4
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