Scalable digit-serial processor array architecture for finite field division

This paper presents a novel scalable digit-serial processor array structure to perform division based on the Stein's division algorithm. The proposed processor array structure enables us to control the number of processing elements as well as the latency of the division operation. This makes us have more flexibility to control the area complexity and the time performance of the divider compared to the previously reported designs. Thus, the presented processor array structure can achieve the time performance requirement of a certain application with minimum hardware resources. The obtained results of the presented design and the previously published competitors' designs indicate that the presented design has a lower area-time product, for bus widths greater than or equal to 26-bits, by percentages ranging from 1.6% to 99% and has a lower energy consumption, for bus widths greater than or equal to 24-bits, by percentages ranging from 4.8% to 99.4% of the compared competitor designs.