Design and Implementation of a Low-Complexity RAKE Receiver and Channel Estimator for DS-UWB

被引：3
|
作者：
Thomos, Christos [1 ]
Papadopoulos, Charalampos [1 ]
Kalivas, Grigorios [1 ]
机构：
[1] Univ Patras, Dept Elect & Comp Engn, Appl Elect Lab, GR-26110 Patras, Greece
来源：
MELECON 2010: THE 15TH IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE | 2010年
关键词：
PERFORMANCE;
D O I：
10.1109/MELCON.2010.5476334
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, the design and implementation of a low complexity Direct Sequence Ultra-Wideband (DS-UWB) receiver subsystem which incorporates a Channel Estimator (CE) and a novel hybrid Partial/Selective (HPS) RAKE Receiver (RR) using maximal ratio combining (MRC) is presented. The proposed architecture demonstrates the tradeoff between energy capture, performance and receiver complexity by combining the benefits of both partial and selective RAKE receiver algorithms. We focus our work on a highly parallel, modular, synthesizable design which is based on FPGA technology and it is optimized for high performance.
引用
收藏
页码：93 / 98
页数：6
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