Programmable implementation of time-area efficient Elliptic Curve Cryptography for entity authentication

被引:3
|
作者
Arunachalam, Kamaraj [1 ]
Perumalsamy, Marichamy [2 ]
机构
[1] Mepco Schlenk Engn Coll, Dept ECE, Sivakasi, India
[2] PSR Engn Coll, Dept ECE, Sivakasi, India
来源
INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS | 2022年 / 52卷 / 02期
关键词
Urdhva Tiryagbhyam; Pipeline; Remote Keyless system Authentication; FPGA; REMOTE USER AUTHENTICATION; FPGA IMPLEMENTATION; POINT MULTIPLICATION; PROCESSOR; CRYPTOSYSTEM; LIGHTWEIGHT; SCHEME; DESIGN;
D O I
10.33180/InfMIDEM2022.203
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The rise of wireless technologies, communications and devices, has resulted in the demand for effective security with low hardware requirements and high speed. Among the various cryptographic algorithms, the Elliptic Curve Cryptography (ECC) provides an attractive solution for this demand. In this paper, the Remote Keyless system (RKE) Authentication process using the ECC is implemented in Field Programmable Gate Array (FPGA). The designed ECC processor supports 256-bit point multiplication and point addition on the Koblitz curve secp256k1. The scalar multiplication is performed with the faster multiplier Urdhva Tiryagbhyam (UT). Additionally, pipelining is incorporated in order to speed up the multiplication process of the processor. The proposed ECC processor performs single point multiplication of 256-bit in 1.2062ms with a maximum clock frequency of 192.5MHz, which provides 212.23kbps throughput and occupies 8.23k slices in Virtex-7 FPGA. Incorporating a pipeline in scalar multiplication improves the maximum clock frequency up to 15.12%, which reduces time consumption by 22.36%, which in turn increases the throughput by 22.36%. The proposed pipelined Vedic multiplier based ECC processor outperforms the existing designs in terms of area, operating frequency, area-delay product and throughput. Also, the security evaluation and analysis of the proposed ECC processor are performed, which ensures the safety of RKE systems. Hence, the implementation of the proposed method offers time-area-efficient and fast scalar multiplication with effective hardware utilization without any compromise in security level.
引用
收藏
页码:89 / 103
页数:15
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