A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver

被引：18

作者：

Wu, Jiangfeng ^{[1
,2
]}

Cusmai, Giuseppe ^{[1
]}

Chou, Acer Wei-Te ^{[1
]}

Wang, Tao ^{[1
]}

Shen, Bo ^{[1
]}

Periasamy, Vijayaramalingam ^{[1
]}

Hsieh, Ming-Hung ^{[1
,3
]}

Chen, Chun-Ying ^{[1
]}

He, Lin ^{[1
]}

Tan, Loke Kun ^{[1
]}

Padyana, Aravind ^{[1
]}

Yang, Vincent Cheng-Hsun ^{[3
]}

Unruh, Gregory ^{[1
]}

Wong, Jackie Koon Lun ^{[1
]}

Hung, Bryan Juo-Jung ^{[1
]}

Brandolini, Massimo ^{[1
]}

Lin, Maco Sha-Ting ^{[3
]}

Chen, Xi ^{[1
]}

Ding, Yen ^{[3
]}

Ko, Yen-Jen ^{[3
]}

Shin, Young J. ^{[1
]}

Hung, Ada Hing T. ^{[1
]}

Chen, Binning ^{[1
]}

Dang, Cynthia ^{[1
]}

Lakshminarasimhan, Deepak ^{[1
]}

Liu, Hong ^{[1
]}

Lin, Jerry ^{[1
]}

Lai, Kowen ^{[1
]}

Wassermann, Larry ^{[1
]}

Shrivastava, Ayaskant ^{[1
]}

Hsiao, Chi-Ming ^{[3
]}

Huang, Chun-Sheng ^{[3
]}

Chen, Jianlong ^{[1
]}

Krishnan, Lakshminarasimhan ^{[1
]}

Wang, Ning-Yi ^{[1
]}

Su, Pin-En ^{[1
]}

Li, Tianwei ^{[1
]}

Shih, Wei-Ta ^{[3
]}

Yang, Yau-Cheng ^{[3
]}

Cangiane, Pete ^{[1
]}

Perlow, Randall ^{[1
]}

Ngai, William ^{[1
]}

Huang, Hanson Hung-Sen ^{[3
]}

Chang, James Y. C. ^{[1
]}

Jiang, Xicheng ^{[1
]}

Venes, Ardie ^{[1
]}

Gomez, Ramon ^{[1
]}

机构：

[1] Broadcom Corp, Irvine, CA 92617 USA

[2] Tongji Univ, Coll Elect & Informat Engn, Shanghai 201804, Peoples R China

[3] Broadcom Corp, Hsinchu 30072, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2016年 / 51卷 / 04期

关键词：

Analog-to-digital converter (ADC); digital compensation; digital phase-locked loop (PLL); digital signal processing (DSP); digitally assisted analog; direct sampling; full-band capture (FBC); ADC; TDC; PLL;

D O I：

10.1109/JSSC.2015.2511164

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 mu m BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies 1 mm(2) area while consuming 300 mW. The LNA consumes 130 mW and occupies 3 mm(2) area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.

引用

页码：845 / 859

页数：15

共 9 条

[1] A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver
Wu, Jiangfeng
Cusmai, Giuseppe
Chou, Acer
Wang, Tao
Shen, Bo
Periasamy, Vijayaramalingam
Hsieh, Ming-Hung
Chen, Chun-Ying
He, Lin
Tan, Loke
Padyana, Aravind
Yang, Cheng-Hsun
Unruh, Gregory
Wong, Jackie
Hung, Juo-Jung
Brandolini, Massimo
Lin, Sha-Ting
Chen, Xi
Ding, Yen
Ko, Yen-Jen
Shin, Young
Hung, Ada
Chen, Binning
Dang, Cynthia
Lakshminarasimhan, Deepak
Liu, Iris
Lin, Jerry
Lai, Kowen
Wassermann, Larry
Shrivastava, Ayaskant
Hsiao, Chi-Ming
Huang, Chun-Sheng
Chen, Jianlong
Krishnan, Lakshminarasimhan
Wang, Ning-Yi
Su, Pin-En
Li, Tianwei
Shih, Wei-Ta
Yang, Yau-Cheng
Cangiane, Pete
Perlow, Randall
Ngai, William
Huang, Hung-Sen
Chang, James Y. C.
Jiang, Xieheng
Veries, Ardie
Gomez, Ramon
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (04) : 832 - 844
[6] Full-band direct-conversion receiver with enhanced port isolation and I/Q phase balance using microwave photonic I/Q mixer
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[8] A CMOS 4-Channel MIMO Baseband Receiver with 65dB Harmonic Rejection over 48MHz and 50dB Spatial Signal Separation over 3MHz at 1.3mW
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