Optimization of LNS operations for embedded signal processing applications

This paper introduces an optimization technique for the design of logarithmic arithmetic-based embedded signal processors. The fundamental concept of the proposed technique is the determination of the optimal values of the logarithmic base b, which minimize the number of memory words required to be stored in look-up tables (LUTs) for the implementation of logarithmic-arithmetic addition and subtraction. The application of the proposed technique is facilitated by an introduced formula, which returns the optimal bases using the equivalent linear word length n as a parameter. Optimal values of b are identified for the cases b < 1 and b > 1 and their performance is compared. The comparison reveals that the absolute minimum of memory words is achieved by selecting particular values of b, b < 1. The proposed technique exploits recently introduced equivalence criteria between linear and logarithmic number representations and it is shown to reduce up to two times the size of the required memory LUT when compared to the conventional choice b = 2, without imposing any overhead on the logarithmic architecture.